Computer systems employ memory address lines which are provided with drive signals in conjunction with the operation of the memories. Memory address signals typically have a very high capacitance load, so that the output buffer for the drive signal must be matched to that load. Even for computers of the same type, the load, however, varies significantly depending upon how much memory is installed in the computer system. A similar load variation occurs for systems with expansion bus provisions.
If the drive signal on the output pad of the integrated circuit providing the memory address drive signal or a bus drive signal is designed to drive the highest capacitive load which may be connected to such an output pad, the signal will be much too strong for the smallest possible capacitive load which could be connected to such an output pad. Obviously, if a system is custom designed and fixed in size, exact matching can be accomplished. The problem, however, exists when the drive circuit is separately manufactured from the memory or bus cards installed in the computer. If the circuit provides a signal which is capable of driving a high capacitive load, such a signal can cause major problems, such as undershoot, ringing and sharp edges for signals applied to small capacitive loads connected to the output bonding pad of the drive circuit.
If the output bonding pad of the drive circuit is designed drive a capacitive load which is between the lowest and highest loads which may be connected to the bonding pad, the signal is too weak for the highest load and still too strong for the smallest load which may be encountered by the drive system. This mismatching again causes problems with the signals applied to the memory address inputs of the computer.
In the past, attempts to solve this problem utilized external buffer circuits to split the capacitive load. This results in additional parts on the circuit board. More power is consumed by the extra parts, and more signals must be routed on the circuit board to direct the signals to the external buffering circuits, In addition, an increased number of signal transitions occur. This inherently causes a noisier environment to exist. Although the necessary matching of the memory address signals to the load of the memory address line of the computer is accomplished with such external buffering, it is not efficiently and efficiency and effectively accomplished because of the above-mentioned disadvantages.
A system which is custom designed to exactly match the load connected to the output pad of the driver has been developed. That system is disclosed in the patent to Asano No. 4,719,369 and is used to "trim" the size of the output buffer to match the pre-established characteristic impedance of a specified impedance transmission line. The buffer is designed to work with a single impedance load, and is not designed to be used with loads having wide range of different impedances. The trimming is accomplished as an internal function of the chip, of which the output buffer amplifiers are a part. The trimming compensates for internal variations, such as voltage, temperature, and process, as these internal variations affect the output circuit part.
To accomplish the internal trimming automatically, the prior art system mentioned above employs four parallel-connected CMOS output buffer amplifiers. The gate width of the transistors in the buffer amplifiers of Asano are constructed, physically, with a ratio of 8:4:2:1. Resistors are fabricated on the chip with the buffer amplifiers to vary in impedance in accordance with voltage and temperature variation to which the chip is exposed. Gate width control circuits sense the variations of the voltages across these control resistors to automatically enable or disable different ones of the output buffer amplifiers to effect the desired trimming to match the output drive characteristics of the circuit with the pre-established impedance of the load to which it is connected. The circuit is fixed in size to initially establish, and to maintain during operation, the exact impedance matching for a particular load. If such a circuit or device, however, were to be installed in a computer to drive a load different from the pre-established load for which it is designed, serious impedance mismatch would occur, since the trimming, which is effected by the Asano system, would not track or follow the variations of such a different load. No independent control of the enabling or disabling of the various parallel connected buffer amplifier circuits is provided.
Consequently, it is desirable to provide a drive signal on an integrated circuit board which may be configured to drive a variable amount of capacitive load without causing undue noise in the system or degrading the speed of the signal.